1. Field of the Invention
The present invention relates generally to apparatus for detection of irregularities in reflective surfaces, and more particularly to an automated method and apparatus for inspecting planar objects such as silicon wafers, painted or polished surfaces, etc., to detect surface non-uniformities.
2. Description of the Prior Art
With increasing demand for integrated circuit devices, manufacturing efficiency and yield become more and more important. In the fabrication of integrated circuits on silicon wafers, a large number of integrated circuits are simultaneously processed during multi-stage operations generally referred to as wafer fabrication or wafer processing. Upon completion of the processing operation, the individual integrated circuits are tested and marked as either acceptable or unacceptable. The wafer is then fractionated into dice or chips, each of which contains one of the integrated circuits, and the chips which have passed inspection are packaged to provide usable IC devices. However, numerous processing steps are required during the wafer processing operation, and during any step process variations may occur which can result in irregularities that materially affect the yield of the wafer. It is therefore desirable to have means available for inspecting the wafer at various points during the processing sequence so that system faults can be discovered and abated, and ultimately, yield optimized.
In general, the geometry of the various integrated circuit components formed in the wafer surface are defined by a photolithographic process wherein an oxide layer is initially grown on the wafer surface, a thin layer of photo-sensitive resist material is deposited over the oxide layer, and the resist layer is exposed to high-intensity ultraviolet light through a pattern mask which defines (1) areas of the wafer which will remain covered or masked and (2) areas which will be uncovered during subsequent processing steps, which might include coating by various means such as spin-coating, deposition (CVD), and etching by various means including the application of chemical etching and plasma etching techniques. These processes are normally repeated a number of times during the fabrication of a silicon wafer to develop the multiple layers of integrated circuit components. It is not unusual for a silicon wafer to undergo 20 or more processing iterations before the fabrication operation is completed.
A problem that may occur during any of the several coating and etching steps is that of resist-burning of the wafer surface. The actual cause of resist-burning is not completely understood, but the factors that contribute include (1) non-uniform cooling of the wafer, (2) uneven flow of gas in the processing chamber, (3) non-uniform or incorrect temperature of the processing chamber, (4) non-uniform cooling under the wafer, and (5) variations in voltage during processing. Such resist-burning causes inconsistent patterning of integrated circuit components and distortion of line width formations in the burned regions. When resist burns occur, it is not uncommon to find regions of the wafer in which line widths of, for example, 0.5.mu. may be distorted to as much as 0.8.mu.. The inconsistent patterning and distorted line widths that result may affect circuit operation and may even render the integrated circuits formed in the burned regions to be inoperable.
Heretofore, silicon wafers have been visually inspected for resist burns. At certain light reflection angles, resist burn regions of a wafer appear darker than normal regions that are not resist-burned. To inspect a wafer, an operator would typically pick up the wafer with tweezers, reflect light off the surface, and look for regions which were discolored or experienced irregular reflection. However, such visual inspections are not reliable and normally are not specific enough to allow any more than a gross GO or NO-GO decision to be made. When a resist-burned region is found, the operator may elect to mark the region or discard the wafer entirely. If the wafer is not discarded, it is important to mark the defective regions because later processing steps may mask the burned region or regions so that the defective portions of the wafer will appear normal upon later inspection.
In an attempt to prevent resist burns, processing equipment has heretofore been periodically inspected and carefully maintained. For instance, before a work shift, a processing chamber may be taken off line to run test wafers. After the test wafers are processed, they are examined at the microscopic level, and line width measurements may be taken to ensure proper operation of the processing chamber. After verification, the chamber is then placed back on line to process actual production wafers, but this verification process may take as much as an hour or more of time that could otherwise be spent processing the wafers. Since no devices are commercially available for detecting resist burns on the production line, off-line verification of the processing equipment is the best technique available for reducing the occurrence of the resist-burning phenomena and thus avoiding substantial reductions in yield of processed wafers.
It is therefore desirable that in-line inspection apparatus be provided for automatically inspecting and detecting the resist burns on silicon wafers occurring during the production process.